An integrated circuit (IC) may include circuitry or logic elements that may be used to perform any of a variety of functions. An IC may be formed by multiple interconnecting metal and via layers. Signals, including power and ground signals, are routed to different parts of the IC via signal routing networks formed within the multiple metal and via layers in the IC. Various networks such as signal, clock and power networks may be formed to connect different circuitry within the IC.
Typically, an IC is packaged to protect internal circuitry from external contamination or physical damage. An IC package generally includes an IC die placed on a substrate. Interconnects such as bumps (e.g., controlled collapse chip connection bumps) on a surface of the IC die (e.g., such as a flip-chip die) may electrically connect the IC die to the substrate that it is placed on. Such an IC may be connected to other circuit elements, such as a memory module or even another IC, when used as part of a larger system.
Signals, including clock signals, may be transmitted from or received by the IC via the bumps. Power supply may generally be provided by an external source to the IC. For example, a power source (e.g., Vcc or ground voltage) may be connected to the IC via the bumps on the IC. Power lines or metal straps are formed in the various metal layers in the IC to connect circuitry within the IC to the bumps.
Generally, the power lines may be formed in at least two different metal layers and arranged in a mesh pattern with some of the power lines extending across the bumps on the IC. As the power lines extend across the bumps, the power lines may form a shared power network in the IC. This may lead to higher voltage drop for circuitry in the periphery region of the IC. For example, input-output circuitry placed at the periphery region of the IC may experience higher voltage drop as they are farther away from the core region (where the bumps are located) of the IC. Power lines that are arranged across bumps on the IC may also cause uneven current distribution between the bumps that may subsequently degrade performance of the device or reduce the life cycle of the device.
It is within this context that the embodiments described herein arise.